In recent years, an MR element has been widely used as an element for use in a head of a magnetic recording medium such as a hard disk drive, a floppy disk drive or the like. The head using the MR element has a large reproduction output as compared with a head using a conventional thin film element. Further, this head is capable of largely improving surface recording density of the magnetic recording medium.
The MR element according to the present invention refers to elements as a whole showing a magneto-resistive effect wherein the resistance changes with an application of an outside magnetic field. For example, the MR element includes a GMR (giant magneto-resistive) element or a TMR (tunneling magneto-resistive) element.
FIG. 9 shows an MR bias current circuit on the conventional read amplifier circuit input stage described in the Japanese Patent Application Laid-Open No. 11-7601.
In FIG. 9, reference numeral 1 denotes an MR element, 2 a differential amplifying circuit, 3 a feed-back circuit, 4a and 4b lowpass filters, 5a and 5b MOS transistors, 6a and 6b rectified current circuits, 7a and 7b capacitors, and 8a, 8b, 16 and 17 resistors.
Advantages and operations of the conventional technology are explained below. The bias current Imr of the MR element 1 is set in the following manner.
A PMOS transistor M2 and an NMOS transistor M8 are arranged on both ends of the MR element 1. A rectified current Ib that is supplied from the rectified current source 6a is allowed to flow to the NMOS transistor M4 that is diode connected. The NMOS transistor M4 and the NMOS transistor M8 constitute a current mirror circuit, and MR bias current Imr which depends on the rectified current Ib is allowed to flow to the NMOS transistor M8. The NMOS transistor M4 and the NMOS transistor M6 constitute the current mirror circuit, and the rectified current Im6 is allowed to flow to the NMOS transistor M6. The rectified current Im6 is allowed to flow from the PMOS transistor M1 which is diode connected. Sum of the rectified current Im6 and the collector current Iq1 of the NPN transistor Q1 represented by an expression Im1=Im6+Iq1 flows through the PMOS transistor M1. A current which is the same as the MR bias current Imr which flows through the NMOS transistor M8 flows through the PMOS transistor M1 and the PMOS transistor M2 which constitute the current mirror circuit.
On the node A to which the gate terminals of the PMOS transistor M1 and the PMOS transistor M2 are connected, a lowpass filter 4a which comprises the resistor 8a and the capacitor 7a is arranged so that a noise of the gate voltage of the node A is eliminated and the noise of the MR bias current Imr is lowered. The input impedance of the MOS transistor of the power source is sufficiently large because of the characteristics of the MOS transistor so that a combination of the lowpass filter can be realized which can decrease the capacitance by enlarging the resistance. The capacitance of the lowpass filter can be incorporated in the semiconductor apparatus. In a similar manner, the gate voltage of the node B is such that the noise component is removed with the lowpass filter 4b which comprises the resistor 8b and the capacitor 7b, and the noise of the MR bias current Imr is lowered.
The bias current Imr of the MR element 1 which is set in this manner is such that the resistance of the MR element 1 changes in accordance with a signal from a magnetic disc which is not shown here, and the voltage difference between the two ends of the MR element 1 is input to the differential amplifying circuit 2. The differential amplifying circuit 2 sets the direct current-like differential output voltage to zero so that only the alternate current-like component is amplified to be output to the latter stage circuit.
Furthermore, along with an increase in the density of the magnetic disc apparatus, a distance between the MR head for detecting the magnetic signal and the magnetic disc becomes very small (1 .mu.m or less) so that the MR head and the magnetic head contact each other very frequently. Since the DC voltage of the MR element changes according to the MR bias current Imr, there is a fear that an over-current flows through the MR element at the time of the short circuit of the MR element and the GND potential (which occurs when the MR head and the magnetic disc contact each other) with the result that the MR element is damaged. As a countermeasure against such phenomenon, the mid-point potential of the MR element is maintained at the GND potential in the following manner.
The node C, which is equal to the mid-point potential of the MR element because of the two resistors 16 and 17 which have the same size, is connected to one of the input terminals of the differential amplifying circuit which constitutes a feed-back circuit 3 while the other input terminal of the differential amplifying circuit is connected to the GND potential. The feed-back circuit 3 comprises a pair of NPN transistors Q1 and Q2 and the current source 6b. The collector of Q1 is connected to the node D while the collector of Q2 is connected to Vcc line. When the potential of node C is higher than the GND potential, the collector currents Iq1 of Q1 and Im1 decrease and the MR bias current which flows through the transistor M2 decreases with the result that the potential of the node C is lowered and is maintained at the GND potential. On the contrary, when the potential of the node C is lower than the GND potential, currents Iq1 and Im1 increase and the MR bias current increases with the result that the potential of the node C rises and is maintained at the GND potential.
The conventional MR element signal amplifying circuit is constituted in the manner described above, and it is required that the MOS transistors M2 and M8 which allow the MR bias current Imr to flow should be of relatively larger size because a current of the order of several mA is required to flow as the MR bias current Imr. If the MOS transistors M2 and M8 have a large size, since the drains of the MOS transistors M2 and M8 are connected to the two terminals of the MR element, capacitance between the drain and the gate of the MOS transistors M2 and M8, namely a parasitic capacitance, is generated between the drain and the substrate. Thus, there arises a disadvantage that the frequency characteristic in a high frequency region is deteriorated.